Interrupts are events that interrupt the execution of a program from an external source. Interrupts are divided into maskable interrupts and non-maskable interrupts (NMI) i.e. reset. Exceptions are events that interrupt the execution of a program that are generated by the program execution. For example dividing a number by zero would generate a "Zero Division" exception. Otherwise interrupts and exceptions are almost identical. But interrupts take precedence over exceptions. The v810 handles interrupts and exceptions through an interrupt table. When a given interrupt/exception is generated the current PC and PSW registers are saved in the EIPC/EIPSW registers. And when a NMI or Duplexed exception is generated the PC and PSW are stored in the FEPC/FEPSW registers. Next the exception cause register (ECR) is filled in with the interrupt/exception number, the PSW Int Level is set to 1+current interrupt level, the PSW EP and ID bits are set to 1 and the PC is updated to point to the interrupt handler vector.

In order for a maskable interrupt to occur the NP bit of the PSW must be 0, the EP bit of the PSW must be zero, the ID bit of the PSW must be zero. And the interrupt being fired must have an id greater than or equal to the Interrupt Level stored in the PSW.

Table 1: Interrupt/Exception Table

The v810 is not set up to handle more than one interrupt at a time, it can handle up to 2 exceptions. In order to support multiple interrupts at a time your interrupt code must:
- disable all further interrupts by setting the ID bit of the PSW to 1
- save the EIPC and EIPSW registers
- clear the EP bit from the PSW
- finally re-enable interrupts by setting the ID bit to 0 in the PSW

Homebrew